GitHub

Best Practice Guide for SystemVerilog DPI Component Generation

HDL Verifier™ facilitates the generation of SystemVerilog DPI and Universal Verification Methodology (UVM) testbench components directly from MATLAB® or Simulink®, bridging the gap between algorithm ...
GitHub

SystemVerilog Functional Coverage for RISC-V ISA

This project is a work in progress (started in early 2022) to provide the RISC-V Verification ecosystem and users an immediate solution to SystemVerilog Functional Coverage for the RISC-V ISA. The ...
IEEE

Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

Abstract: Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number ...
IEEE

VFlow: Discovering Optimal Agentic Workflows for Verilog Generation

Abstract: Hardware design automation faces challenges in generating high-quality Verilog code efficiently. This paper introduces VFlow, an automated framework that optimizes agentic workflows for ...